Proceedings of the Eighth International Workshop on Constraint Handling Rules

The aim of this talk is to present a general framework for compiling Constraint Handling Rules (CHR) to a low level hardware description language (HDL). The benefit introduced by a CHR based hardware synthesis is twofold: it increases the abstraction level of the common synthesis work-flow and it can give significant speed up to the execution of a CHR program. I will describe a practical method that set CHR as starting point for a hardware description and afterwards I will show how to integrate the generated hardware code, deployed in a Field Programmable Gate Array (FPGA), within the traditional software execution model of CHR. The result is a prototype CHR execution engine composed of a general purpose processor coupled with a specialized hardware accelerator. The former executes a CHR specification while the latter unburdens the processor by executing in parallel the most computational intensive rules. The talk will have a practical focus, illustrating the achieved performance obtained by a prototype system architecture. The motivations that gave rise to the development of a novel technique to synthesize behavioral hardware components starting from a declarative programming language are basically two. Firstly it introduces a high level of abstraction in an environment that is traditionally described at low level and then secondly it results in hardware blocks that can be interfaced with the high level language execution giving relevant time improvements. Therefore we developed a completely general framework that allows to synthesize reconfigurable hardware easily employable in a wide range of application, since a small modification to the high level code affects a huge portion of low level HDL code (resulting in a remarkable time saving for the programmer). Moreover the generated hardware code is fully compliant with the commonly adopted ones and hence can be easily integrated in the existing hardware project. Once hardware can be directly compiled from a high level language, we implemented a coupled system constituted by a traditional general purpose CPU and a hardware accelerator deployed on a Field Programmable Gate Array (FPGA). Thus such sole system will be compiled from a single high level language specification through a double compilation path resulting in a efficient execution engine. In the following paragraphs we briefly introduce our contributions to the two aforementioned research areas. High Level Synthesis The ability to integrate an ever greater number of transistors within a chip and the consequent complexity growth of the features that